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Author: Admin | 2025-04-28
Base array , and the smallestelement that is replicated to make the basearray is the base cell (sometimes called aprimitive cell ).Dr.YNM 17 18. Contd…• Only the top few layers of metal, which definethe interconnect between transistors, aredefined by the designer using custom masks.To distinguish this type of gate array fromother types of gate array, it is often called amasked gate array ( MGA ).• The designer chooses from a gate-array libraryof predesigned and pre-characterized logiccellsDr.YNM 18 19. Contd…• The logic cells in a gate-array library are oftencalled macros . The reason for this is that thebase-cell layout is the same for each logic cell,and only the interconnect (inside cells andbetween cells) is customized, which is similarto a software macro.Dr.YNM 19 20. Types of MGA or Gate-array based ASICs• There are three types of Gate Array basedASICs.• Channeled gate arrays.• Channelless gate arrays.• Structured gate arrays.Dr.YNM 20 21. Channeled gate arrays• The channeled gate array was the first to bedeveloped . In a channeled gate array space isleft between the rows of transistors for wiring.• A channeled gate array is similar to a CBIC.Both use the rows of cells separated bychannels used for interconnect. One differenceis that the space for interconnect betweenrows of cells are fixed in height in a channeledgate array, whereas the space between rows ofcells may be adjusted in a CBIC.Dr.YNM 21 22. A channeled gate-array dieDr.YNM 22 23. Features of MGA• Only the interconnect is customized.• The interconnect uses predefined spacesbetween rows of base cells.• Manufacturing lead time is between two daysand two weeks.Dr.YNM 23 24. Channel less Gate Array• This channel less gate-array architecture is nowmore widely used . The routing on a channellessgate array uses rows of unused transistors.• The key difference between a channel less gatearray and channeled gate array is that there areno predefined areas set aside for routingbetween cells on a channel less gate array.Instead we route over the top of the gate-arraydevices. We can do this because we customizethe contact layer that defines the connectionsbetween metal 1, the first layer of metal, andthe transistors.Dr.YNM 24 25. Features of Channel less Gate Array• Only the interconnect is customized.• The interconnect uses predefined spacesbetween rows of base cells.• Manufacturing lead time is around two days totwo weeks.• When we use an area of transistors for routingin a channel less array, we do not make anycontacts to the devices lying underneath , wesimply
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